VLSI & semiconductor design engineer — full-custom CMOS from schematic to silicon, DRC/LVS sign-off, and analog front-ends that hold their gain.
// About
An Electronics & Communication Engineering student at NIT Goa (CGPA 9.55) working across the full-custom VLSI flow — transistor-level schematic, layout, and DRC/LVS sign-off in Cadence Virtuoso & Assura. I've built an 8-bit ALU whose novel logic cell was accepted at IEEE NEWCAS 2026, and tuned a 108 dB analog front-end as a research intern at IIT Madras.
CurrentlyFinal-year B.Tech ECE at NIT Goa · full-custom VLSI & analog front-end design
// 02 — Focus
Schematic capture → transistor-level design → layout → post-layout verification in Cadence Virtuoso.
DRC / LVS sign-off in Assura; resolving layout-rule violations through to a clean tape-out-ready cell.
Comparators, multi-stage amplifiers, biasing schemes, impedance matching and signal-integrity tuning.
ALUs, an 8-bit CPU and custom ISAs in Verilog — the logic side of the same silicon story.
// 03 — Projects
Full-custom VLSI, analog front-ends, a CPU built from scratch — and a little applied ML on the side.
A CMOS dynamic comparator with full input common-mode range. ~100 ps lower propagation delay than traditional designs while holding comparable kickback noise and offset. Pre-layout simulation + corner analysis.
Transistor-level 8-bit ALU taken through the full-custom flow — schematic to post-layout, DRC/LVS clean in Assura — supporting 15 operations. Introduced a novel logic cell delivering ~88 µW power and ~200 ps delay improvement over standard CMOS.
Three-stage high-gain, wideband amplifier for a DAS system — 108 dB gain over 100 MHz bandwidth, paired with a balanced photodetector. Parasitic mitigation, bias stabilisation, and ±5% inter-stage impedance matching.
An 8085-inspired 8-bit CPU: custom instruction set, a compiler built in Excel VBA, an ALU (7 ops), a hardwired control unit and 4 general-purpose registers — verified across 10+ custom programs.
An AI pipeline detecting Chagas disease from 12-lead ECG — scalograms, HRV/statistical features and Tucker decomposition, with SMOTE balancing, metadata augmentation and patient-wise evaluation.
A low-power 1 MHz (MW-band) AM transmitter with stable transmission over 6–8 ft, plus a compact high-voltage EMP generator demonstrating controlled disruption of nearby electronics within 0.1–0.2 m.
// 04 — Experience
Chennai, India · on-site
// Education
B.Tech, Electronics & Communication Engineering
CGPA 9.55 / 10 · Minor in Computer Science (CGPA 9.61 / 10)
CBSE — Computer Science (Class XII)
GPA 10 / 10 · Physics topper · Class X: 93%
// 05 — Toolbox
EDA & simulation
HDL & languages
Domains
Applied ML
// 06 — Recognition
Novel logic cell accepted for presentation at IEEE NEWCAS 2026.
Merit selection — top 11.8% of 255 students for the CSE minor.
Certificate of Distinction (A1 in all subjects, Class XII) among 624 students.
Physics topper & 3rd in stream (Class XII) among 624 students.
Featured in The Gulf Daily News & The Daily Tribune (Bahrain) for academic excellence.
Finalist, All-India SASTRA-Pratibha Technology Competition (among 100,000 students).
// 07 — Contact
Open to VLSI, physical-verification and analog roles — email or LinkedIn is fastest.
Open to